The present invention relates in general to methods for forming semiconductor structures, and more particular to methods for forming a dielectric layer within trenches.
As the device density on integrated circuits continues to increase, the size and distance between device structures continue to decrease. The narrower widths in the gaps of the structures and the trenches between structures increases the ratio of height to width (i.e., the aspect ratio) in these formations. The continued miniaturization of integrated circuit elements is shrinking the horizontal width within and between these elements faster than their vertical height.
While the ability to make device structures with ever increasing aspect ratios has allowed more of the structures (e.g., transistors, capacitors, diodes, etc.) to be packed onto the same surface area of a semiconductor chip substrate, it has also created fabrication problems. One of these problems is the difficulty of completely filling the gaps and trenches in these structures without creating a void or seam during the filling process. Filling gaps and trenches with dielectric materials like silicon oxide is necessary to electrically isolate nearby device structures from each other. If the gaps were left empty, there would be too much electrical noise, and current leakage for the devices to operate properly (or at all).
When gap widths are larger (and aspect ratios smaller), the gaps are relatively easy to fill with a rapid deposit of a dielectric material. The deposition material would blanket the sides and bottom of the gap and continue to fill from the bottom up until the crevice or trench was fully filled. As aspect ratios increased however, it became more difficult to fill the deep, narrow trench without having a blockage start a void or seam in the fill volume.
Voids and seams in a dielectric layer create problems both during semiconductor device fabrication and in the finished devices. The voids and seams are formed randomly in the dielectric layer and have unpredictable sizes, shapes, locations and population densities. This results in unpredictable and inconsistent post-deposition processing of the layer, such as even etching, polishing, annealing, etc. The voids and seams in the finished devices also create variations in the dielectric qualities of gaps and trenches in device structures. This can result in uneven and inferior device performance due to electrical crosstalk, charge leakage, and even shorting within and between device elements.
Techniques have been developed to minimize the formation of voids and seams during deposition of dielectric materials on high aspect ratio structures. These include slowing the deposition rate of the dielectric material so it stays more conformal to the sidewalls and bottom of the trench. A more conformal deposition can reduce the degree to which the deposited material builds up at the top or middle of the trench and eventually seals off the top of a void. However, slowing the deposition rate means increasing the deposition time, which reduces processing efficiency and production rates.
Another technique to control void formation is to increase the flowability of the deposited dielectric material. A material with more flowability can fill the trenches quickly from bottom up, and this desirably prevents void or seam formation that would become a permanent defect in the fill volume. Increasing the flowability of a silicon oxide dielectric material often involves adding water vapor or peroxide (e.g., H2O2) to the mix of precursors used to form the oxide layer. The water vapor creates more Si—OH bonds in the deposited film which impart an increased flowability to the film. However, increasing the moisture level during a silicon oxide deposition can also adversely effect the properties of the deposited film, including its density (i.e., an increased wet etch rate ratio (WERR)) and dielectric properties (i.e., an increased k-value).